It is known that a radiofrequency signal is synthesized by a frequency synthesizer the purpose which is to generate a sinusoidal signal SLO 
When the system is in reception mode, this sinusoidal signal SLO will combine with a received analog signal to allow recovery of encoded information carried by the latter.
When the system is in emission mode, this sinusoidal signal SLO will combine with an analog signal generated by a digital signal containing the said information.
Depending on the field of application of a system for converting a radiofrequency signal, the design of the latter will require that all or part of the following criteria are met:                Purity: the purity or spectral purity characterizes the quality of signal SLO generated by the frequency synthesizer. The more the signal SLO contains signals for conversion other than the ideal sinusoidal signal S0 (harmonics or different tone signals), the more the performances of the conversion system will be degraded.        Phase noise: the phase noise characterizes the random gap between the signal phase SLO actually generated by the frequency synthesizer and the ideal sinusoidal signal phase S0 for conversion.        The cost: the cost of a radiofrequency signal conversion system is closely related to the surface of silicon that it occupies. Therefore, this occupied surface will have to be minimized in order to reduce the cost of the radiofrequency signal conversion system.        
In order to generate a sinusoidal signal SLO, several types radiofrequency signal synthesizing systems have been proposed. These types of synthesizing system use frequency synthesizers that can be grouped into two main families: analog frequency synthesizers with phase-locked loop generally designated by PLL and all digital phase-locked loop synthesizers generally designated by their acronym ADPLL.
A conventional PLL-type frequency synthesizer consists of a voltage controlled oscillator, usually designated by VCO the role of which is to generate a sinusoidal signal SLO. It also includes a high frequency divider that can divide the frequency of signal SLO by a factor N. A phase comparator determines the gap between the signal phase at the divider output and the phase of a reference signal with known and stable frequency. This reference signal SRef is usually generated by a crystal oscillator or quartz oscillator. The phase comparator generates a signal Vctrl that reflects the said phase gap. Signal Vctrl is then filtered by a low-pass filter before being injected into the VCO. Thus the loop converges so that the frequency generated by the VCO approaches the reference signal frequency SRef multiplied by N.
All the frequencies that can be obtained with this type of PLL at the VCO output consist of all the reference signal SRef frequencies multiplied by N. Therefore, a reference signal with a frequency equal to the gap between the channels to be used (generally a few KHz to a few MHz) should be used.
To circumvent this constraint concerning the reference frequencies, PLL-type frequency synthesizers have been proposed with a frequency divider whose division ratio can be modulated on a few values centered on the main division ratio N. The frequencies that can be attained are no longer limited to the reference signal frequencies SRef multiplied by N.
However, such a frequency divider tends to generate a noise, which involves a limitation on the PLL bandwidth. This noise can only be reduced by substantial energy overconsumption by the divider.
A digital frequency synthesizer ADPLL consists of a VCO whose output is converted into a digital signal by an analog/digital converter. The ADPLL also includes a frequency digital divider, a digital phase comparator, a digital low-pass filter and digital/analog converter arranged successively from the analog/digital converter output to the VCO in order to create a digital loop. The digital divider divides the digital signal frequency generated by the analog/digital converter. The digital phase comparator determines the gap between the signal phase at the divider output and a reference signal phase and generates a digital signal Vctrl reflecting the said phase gap.
Signal Vctrl is then filtered by the digital low-pass filter before being converted into an analog signal by the digital/analog converter. The analog signal is then injected into the VCO.
In other types of ADPLLs, digital signal Vctrl from a digital phase converter and a digital low-pass filter modulate a digitally controlled oscillator. This type of oscillator is generally designated by its acronym DCO (Digitally Controlled Oscillator). Its input is a digital signal. Advantageously, the ADPLL provides for both a VCO and a DCO.
In known ADPLLs, the phase comparator usually generates significant noises and these are constraining for the filter bandwidth. Known ADPLLs require a compromise between purity and agility, the agility being closely related to the width of the filter bandwidth. Moreover, known ADPLLs cannot generate high frequencies typically above 3 GHz. It results from these constraints that the use of known ADPLLs is today limited to a few very specific applications.
Moreover, the quality of the digital/analog converter directly affects the VCO input signal. In fact, the performances of known digital/analog converters cannot generate a signal that is sufficiently accurate to obtain a satisfactory level of purity at the frequency synthesizer output.
In addition, the use of a DCO considerably limits the accuracy of modulation in the ADPLL type frequency synthesizers.